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preliminary this is a product that has fixed target specifications but are subject ramtr on international corporation to change pending characterization results . 1850 ramtron drive, colorado springs, co 80921 (800) 545 - fram, (7 19) 481 - 7000 rev. 1.1 http://www.ramtron.com sept. 2011 page 1 of 14 fm 24v01 128 k b serial 3v f - ram memory features 128 k bit ferroelectric nonvolatile ram ? organized as 16,384 x 8 bits ? high endurance 100 trillion (10 14 ) read/writes ? 10 year data retention ? nodelay? writes ? advanced high - reliability ferroelectric process fa st two - wire serial interface ? up to 3.4 mhz maximum bus frequency ? direct hardware replacement for eeprom ? supports legacy timing for 100 khz & 400 khz device id ? device id reads out m anufacturer id & p art id low voltage, low power opera tion ? low voltage operation 2.0 v C 3.6v ? active current 9 0 ? a (typ. @ 100khz ) ? standby current 80 ? a (typ.) ? sleep mode current 4 ? a (typ.) industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green/rohs soic package description the fm 24v01 is a 128 kbit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f - ram is nonvolatile and performs reads and writes like a ram. it provide s reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliabili ty problems caused by eeprom and other nonvolatile memories. the fm 24v01 performs write operations at bus speed. no write delays are incurred. the next bus cycle may commence immediately without the need for data polling. in addition, the product offers write endurance orders of magnitude higher than eeprom. also, f - ram exhibits much lower power during writes than eeprom since write operations do not require an internally elevated power supply voltage for write circuits. these capabilities make the fm 24v 01 ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the combination of features allows more frequent data writing with less overhead for the system. the fm 24v01 provides substantial benefits to users of serial eeprom, yet these benefits are available in a hardware drop - in repla cement. the device is avail able in an industry stan dard 8 - pin soic package using a familiar two - wire (i 2 c) protocol. the device incorporate s a read - only device id that allows the host to determine the manufacturer, product density, and product revision. the device is guaranteed over an industrial temperature range of - 40c to +85c. pin configuration pin name function a 0 - a2 device select address sda serial data/address scl serial clock wp write protect vdd supply voltage vss ground a 0 a 1 a 2 vss vdd wp scl sda 1 2 3 4 8 7 6 5 www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 2 of 14 figure 1. fm 24v01 block diagram pin description pin name type pin description a0 - a2 input device select addres s 0 - 2 : these pins are used to select one of up to 8 devices of the same type on the same two - wire bus. to select the de vice , the address value on the two pins must match the corresponding b its contained in the slave address. the address pins are pulled down internally. sda i/o serial data/ addres s: this is a bi - directional pin for the two - wire interface. it is open - drai n a nd is intended to be wire - or d with other devices on the two - wire bus. the input buffer incorporates a s chmitt trigger for noise immunity and the output driver includes slope control for falling edges. a n external pull - up resistor is required. scl input s er ial clock: the serial clock pin for the two - wire interface. data is clocked out of the part on the falling edge, and in to the device on the rising edge. the scl input also incorporates a schmitt trigger input for noise immunity. wp input write protect: when tied to vdd, addresses in the entire memory map will be write - protected. when wp is connected to ground, all addresses may be written. this pin is pulled down internally. vdd supply supply voltage vss supply ground address latch 2 k x 64 fram array data latch 8 sda counter serial to parallel converter control logic scl wp a 0 - a 2 device id and serial number 8 www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 3 of 14 overview the fm 24v01 is a seria l f - ram memory device . the memory array is logically organized as a 16,384 x 8 bit memory array and is accessed using an industry standard two - wire (i 2 c) interface. functional operation of the f - ram is similar to serial eeprom . the major difference between the fm 24v01 and serial eeprom is f - rams superior write performance. memory architecture when accessing the fm 24v01 , the user addresses 16,384 locations each with 8 data bits. these data bits are shifted serially. the 16,384 addresses are accessed using the two - wire protocol, which includes a slave address (to disting uish other non - mem ory devices) and a 2 - byte address. all 14 address bits are used by the decoder for accessing the memory. the access time for memory operation is essentially zero beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the two - wire bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. that is, by the time a new bus tr ansaction can be shifted into the part, a write operation will be complete. this is explained in more detail in the interface section below. users expect several obvious system benefits from the fm 24v01 due to its fast write cycle and high endurance as c ompared with eeprom. however there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring millise conds to write is vulnerable to noise during much of the cycle. note that it is the users responsibility to ensure that v dd is within data sheet tolerances to prevent incorrect operation. two - wire interface the fm 24v01 employs a bi - directional two - wire bus protocol using few pins or board space. figure 2 illustrates a typical system configuration using the fm 24v01 in a microcontroller - based system. the industry standard two - wire bus is familiar to many users but is described in this section. by conven tion, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling the bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the fm 24v01 always is a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions including start, stop, data bit, or acknowledge. f igure 3 illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the electrical specifications section . figure 2. typical system configuration microcontroller sda scl fm 24 v 01 a 0 a 1 a 2 sda scl fm 24 v 01 a 0 a 1 a 2 vdd r min = 1 . 1 k ohm r max = t r / cbus www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 4 of 14 fig ure 3. data transfer protocol stop condition a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations using the fm 24v01 should end with a stop condition. if an operation is in progress wh en a stop is asserted, the operation will be aborted. the master must have control of sda (not a memory read) in order to assert a stop condition. start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all commands should be preceded by a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm 24v01 for a new operation. if duri ng operation the power supply drops below the specified v dd minimum, the system should issue a start condition prior to performing another operation. data/address transfer all data transfers (including addresses) take place while the scl signal is high. e xcept under the two conditions described above, the sda signal should not change while scl is high. acknowledge the acknowledge takes place after the 8 th data bit has been transferred in any transaction. during this state the transmitter should release th e sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the condition is a no - acknowledge and the operation is aborted. the receiver would fail to ackn owledge for two distinct reasons. first is that a byte transfer fails. in this case, the no - acknowledge ceases the current operation so that the part can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not acknowledge to deliberately end an operation. for example, during a read operation, the fm 24v01 will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). when a read ope ration is complete and no more data is needed, the receiver must not acknowledge the last byte. if the receiver acknowledges the last byte, this will cause the fm 24v01 to attempt to drive the bus on the next clock while the master is sending a new command such as stop. slave address the first byte that the fm 24v01 expects after a start condition is the slave address. as shown in figure 4, the slave address contains the device type or slave id , the device select address bits, a page address bit, and a bit t hat specifies if the transaction is a read or a write. bits 7 - 4 are the device type (slave id) and should be set to 1010b for the fm 24v01 . these bits allow other function types to reside on the 2 - wire bus within an identical address range. bits 3 - 1 are t he device select address bits. they must match the corresponding value on the external address pins to select the devic e. up to eight fm 24v01 device s can reside on the same two - wire bus by assigning a different address to each. bit 0 is t he read/write bit . r/w=1 indicates a read operation and r/w=0 indicates a write operation. high speed mode (hs - mode) the fm 24v01 supports a 3.4mhz high speed mode. a master code (0000 1 xxx b) must be issued to place the device into high speed mode. communication between ma ster and slave will then be enabled for speeds up to 3.4mhz. a stop condition will exit hs - mode. single - and multiple - byte reads and writes are supported. see figures 10 and 11 for hs - mode timings. stop (master) start (master) 7 data bits (transmitter) 6 0 data bit (transmitter) acknowledge (receiver) scl sda www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 5 of 14 figure 4. slave address ad dressing overview after the fm 24v01 (as r eceiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. the address requires two bytes . the complete 14 - bit address is latched internally. each access cause s the latched address value to be incremented automatically. the current address is the value that is held in the latch -- either a newly written value or the address following the last access. the current address will be held for as long as power remains or until a new value is written. reads always use the current address. a random read address can be loaded by beginning a write operation as explained below. after transmission of ea ch data byte, just prior to the acknowledge, the fm 24v01 increments the internal address latch. this allows the next sequential byte to be accessed with no additional addressing. after the last address ( 3fff h) is reached, the address latch will roll over to 0000h. there is no limit to the number of bytes that can be accessed w ith a single read or write operation. data transfer after the address information has been transmitted, data transfer between the bus master and the fm 24v01 can begin. for a read operation the fm 24v01 will place 8 data bits on the bus then wait for an ack nowledge from the master. if the acknowledge occurs, the fm 24v01 will transfer the next sequential byte. if the acknowledge is not sent, the fm 24v01 will end the read operation. for a write operation, the fm 24v01 will accept 8 data bits from the master the n send an acknowledge. all data transfer occurs msb (most significant bit) first. memory operation the fm 24v01 is designed to operate in a manner very similar to other 2 - wire interface memory products. the major differences result from the higher perform ance write capability of f - ram technology. these improvements result in some differences between the fm 24v01 and a similar configuration eeprom during writes. the complete operation for both writes and reads is explained below. write operation all writes begin with a slave address , then a memory address. the bus master indicates a write operation by setting the lsb of the slave address (r/w bit) to a 0 . after addressing, the bus master sends each byte of data to the memory and the memory generates an ack nowledge condition. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap from 3fff h to 0000h. unlike other nonvolatile memory technologies, there is no effective write delay w ith f - ram . since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory cycle occurs in less time than a single bus clock. therefore, any operation including read or write can occur immediately following a write. acknowledge polling, a technique used with eeproms to determine if a write is complete is unnecessary and will always return a ready condition. internally, an actual memory write occurs after the 8 th data bit is tran sferred. it will be complete before the acknowledge is sent. therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8 th data bit. the fm 24v01 uses no page bufferi ng. the memory array can be write - protected using the wp pin . setting the wp pin to a high condition (v dd ) will write - protect all addresses. the fm 24v01 will not acknowledge data bytes that are written to protected addresses. in addition, the address cou nter will not increment if writes are attempted to these addresses. setting wp to a low state (v ss ) will deactivate this feature. wp is pulled down internally. figures 5 and 6 below illustrate a single - byte and multiple - byte write cycles. 1 0 1 0 a2 r/w slave id 7 6 5 4 3 2 1 0 a1 a0 device select www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 6 of 14 figure 5. single byte write figure 6. multiple byte write read operation there are two basic types of read operations. they are current address read and selective address read. in a current address rea d, the fm 24v01 uses the internal address latch to supply the address. in a selective read, the user performs a procedure to set the address to a specific value. current address & sequential read as mentioned above the fm 24v01 uses an internal latch to sup ply the address for a read operation. a current address read uses the existing value in the address latch as a starting place for the read operation. the system reads from the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to a 1 . this indicates that a read operation is requested. after receiving the complete slave address , the fm 24v01 will begin shifting out data from the current address on the next c lock. the current address is the value held in the internal address latch. beginning with the current address, the bus master can read any number of bytes. thus, a sequential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be incremented. each time the bus master acknowledges a byte, this indicates that the fm 24v01 should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to proper ly terminate the read will most likely create a bus contention as the fm 24v01 attempts to read out additional data onto the bus. the four valid methods are: 1. the bus master issues a no - acknowledge in the 9 th clock cycle and a stop in the 10 th clock cycle. this is illustrated in the diagrams below. this is preferred. 2. the bus master issues a no - acknowledge in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. 4. the bus master issues a start in the 9 th clock cycle . if the internal address reaches 3fff h, it will wrap around to 0000h on the next read cycle. figures 7 and 8 below show the proper operation for current address reads. selective (random) read there is a simple technique that allows a user to select a ra ndom address location as the starting point for a read operation. this involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. to perform a selective read, the bus master sends out th e slave address with the lsb set to 0. this specifies a write operation. according to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. after the fm 24v01 acknowledges the address, the bus maste r issues a start condition. this simultaneously aborts s a slave address 0 address msb a data byte a p by master by fm 24 v 01 start address & data stop acknowledge address lsb a s a slave address 0 address msb a data byte a p by master by fm 24 v 01 start address & data stop acknowledge address lsb a data byte a www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 7 of 14 the write operation and allows the read command to be issued with the slave address lsb set to a 1 . the operation is now a current address read. figure 7. current a ddress read figure 8. sequential read figure 9. selective (random) read figure 10. hs - mode current address read figure 11. hs - mode b yte write s a slave address 1 data byte 1 p by master by fm 24 v 01 start address stop acknowledge no acknowledge data s a slave address 1 data byte 1 p by master by fm 24 v 01 start address stop acknowledge no acknowledge data data byte a acknowledge s a slave address 1 data byte 1 p by master by fm 24 v 01 start address stop no acknowledge data s a slave address 0 address msb a start address acknowledge address lsb a s a slave address 1 data byte 1 p by master by fm 24 v 01 start & enter hs - mode address stop & exit hs - mode no acknowledge data s 1 start acknowledge x x x 1 0 0 0 0 hs - mode command no acknowledge s a slave address 0 data byte a p by master by fm 24 v 01 start & enter hs - mode address & data stop & exit hs - mode s 1 start acknowledge x x x 1 0 0 0 0 hs - mode command address msb a address lsb a no acknowledge www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 8 of 14 sleep mode a low power mode called sleep mode is implemented on the fm 24v01 device . the device will enter this low power state when the sleep command 86h is clocked - in. sleep mode entry can be entered as follows: 1. the master sends a start comma nd. 2. the master sends reserved slave id 0xf8 3. the master sends the i 2 c - bus slave address of the slave device it needs to identify . the last bit is a dont care value ( r/w bit ) . only one device must acknowledge this byte (the one that has the i 2 c - bus slave address) . 4. the master sends a re - start command . 5. the master sends reserved slave id 0x86 6. the fm 24v01 sends an ack. 7. the master sends stop to ensure the device enters sleep mode. once in sleep mode, the device draws i zz current, but the device continues to mo nitor the i 2 c pins. once the master sends a slave address that the fm 24v01 identifies, it will wakeup and be ready for normal operation with in t rec (400 ? s max.). as an alternative method of determining when the device is ready, the master can send read or write commands and look for an ack. while the device is waking up, it will nack the master until it is ready. figure 12. sleep mode entry s a p by master by fm 24 v 01 start address stop s a rsvd slave id ( f 8 ) slave address a start address acknowledge rsvd slave id ( 86 ) x www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 9 of 14 device id the fm 24v01 device incorporate s a means of identifying the device by pr oviding three bytes of data, which are manufacturer, product id , and die revision. the device id is read - only . it can be accessed as follows: 1. the master sends a start command . 2. the master sends reserved slave id 0xf8 3. the master sends the i 2 c - bus slave ad dress of the slave device it needs to identify . the last bit is a dont care value (r/w bit ) . only one device must acknowledge this byte (the one that has the i 2 c - bus slave address) . 4. the master sends a re - start command . 5. the master sends reserved slave id 0xf9 6. the device id read can be done, starting with the 12 manufacturer bits , followed by the 9 part id entification bits , and then the 3 die revision bits . 7. the master ends the device id read sequence by nacking the last byte, thus resetting the slave devic e state machine and allowing the master to send the stop command . note : the reading of the device id can be stopped anytime by sending a nack command. figure 1 3 . read device id manufacturer id product id die rev. 11 1 0 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 2 1 0 ramtron density variation 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 n 0 0 0 0 0 0 0 figure 1 4 . manufacturer and product id density: 01h=128 k b , 02h=256k b , 03h=512k b , 04=1m b variation: product id bit 4 = s /n , prod uct id bit 0 = reserved t he 3 - byte hex code for an fm 24v01 will be: 0x00 0x4 1 0x 0 0 s a data byte data byte 1 p by master by fm 24 v 01 start address stop no acknowledge data s a rsvd slave id ( f 8 ) slave address a start address acknowledge rsvd slave id ( f 9 ) a a data byte acknowledge www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 10 of 14 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to + 4.5 v v in voltage on any pin with r espect to v ss - 1.0v to + 4.5 v and v in < v dd +1.0v * t stg storage temperature - 55 ? c to +12 5 ? c t lead lead t emperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model ( aec - q100 - 002 rev. e ) - charged device model ( a ec - q100 - 011 rev. b ) - machine model ( a ec - q100 - 003 rev. e ) 3.5kv 1.25kv 200v package moisture sensitivity level msl - 1 * exception: the v in < v dd +1.0v restriction does not apply to the scl and sda inputs. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. dc operating conditions (t a = - 40 ? c to + 85 ? c, v dd = 2.0 v to 3.6 v unless otherwise specified) symbol parameter min typ max units notes v dd main power supply 2.0 3.3 3.6 v i dd v dd supply current @ scl = 100 khz @ scl = 1 mhz @ scl = 3.4 mhz 90 200 500 1 7 5 40 0 100 0 ? a ? a ? a 1 i sb standby current 8 0 15 0 ? a 2 i zz sleep mode current 4 8 ? a 2 i li input leakage current 1 ? a 3 i lo output leakage current 1 ? a 3 v il input low voltage - 0.3 0.3 v dd v v ih input high voltage 0.7 v dd v dd + 0.3 v v ol1 output low voltage ( i ol = 2 ma, v dd 2.7v) 0.4 v v ol2 output low voltage ( i ol = 150 ? a) 0.2 v r in address input resistance (wp, a2 - a 0 ) for v in = v il (max) for v in = v ih (min) 50 1 k ? m ? 4 notes 1. scl toggling between v dd - 0. 2 v and v ss , other inputs v ss or v dd - 0. 2 v. 2. scl = sda = v dd . all inputs v ss or v dd . stop command issued. 3. vin or vout = v ss to v dd . does not apply to wp, a2 - a 0 pins . 4. the input pull - down circuit is strong er (50k ? ) when the input voltage is below v il and weak (1m ? ) when the input voltage is above v ih . www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 11 of 14 a c parameters (t a = - 40 ? c to + 85 ? c, v dd = 2.0 v to 3.6 v unless otherwise specified) f/s - mode (c l <500pf) hs - mode (c l <100pf) symbol parameter min max min max units notes f scl scl clock frequency 0 1.0 0 3.4 mhz 1 t low clock low period 500 160 ns t high clock high period 260 60 ns 4 t aa scl low to sda data out valid 450 13 0 ns t buf bus free before new transmission 0.5 0.3 ? s t hd:sta start condition hold time 260 160 ns t su:sta start condition setup for repeated start 260 160 ns t hd:dat data in hold 0 0 ns t su:dat data in setup 50 10 ns 3 t r input rise time 120 80 ns 2 t f input fall time 120 80 n s 2 t su:sto stop condition setup 260 160 ns t dh data output hold (from scl @ v il ) 0 0 ns t sp noise suppression time constant on scl, sda 50 5 ns notes : all scl specifications as well as start and stop conditions apply to both read and write o perations. 1. the speed - related specifications are guaranteed characteristic points along a continuous cur ve of operation from dc to f scl (max) . 2. this parameter is periodically sampled and not 100% tested. 3. in hs - mode and v dd < 2.7v, the t su:dat (min.) spec i s 15 ns. 4. in hs - mode and v dd < 2.7v, the t high (min.) spec i s 1 00 ns . capacitance (t a = 25 ? c, f=1.0 mhz, v dd = 3 .3 v) symbol parameter min max units notes c i/o input/output capacitance (sda) - 8 pf 1 c in input capacitance - 6 pf 1 notes 1. this parameter is periodically sampled and not 100% tested. power cycle t iming ( t a = - 40 ? c to +85 ? c, v dd = 2.0 v to 3.6v) symbol parameter min max units notes t vr v dd rise time 50 - ? s/v 1,2 t vf v dd fall time 100 - ? s/v 1,2 t pu power up (v dd min) to first access (start condition) 250 - ? s 3 t pd last access (stop condition ) to power down (v dd min) 0 - ? s t rec recovery time from sleep mode - 400 ? s notes 1. this parameter is characterized and not 100% tested. 2. slope measured at any point on v dd waveform. 3. applies to v dd > 2.7v. when powering up to v dd < 2.7v, the t pu limit i s 500 ? s. www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 12 of 14 ac test conditions equivalent ac test load circuit input pulse levels 0.1 v dd to 0.9 v dd input rise and fall times 10 ns input and output timing levels 0.5 v dd diagram notes all start and stop timing parameters apply to both read and write cycles. clock specifications are identical for read and write cycles. write timing parameters apply to slave address, word address, and write data bits. functional relationships are illustrated in the relevant datasheet sections. these diagrams illustrate the timing parameters only. read bus timing write bus timing data retention ( t a = - 40 ? c to +85 ? c ) parameter min max units notes data retention 10 - years t su:sda start t r ` t f stop start t buf t high 1/fscl t low t sp t sp acknowledge t hd:dat t su:d at t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda 3 . 6 v output 1 . 8 k ohm 100 pf www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 13 of 14 mechanical drawing 8 - pin soic ( jedec standard ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xx x xx= part number , p=package type r=rev code, ll lllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm 24v01 , green/rohs soic p ackage, rev. a, lot 9646447 , year 2010 , w ork week 2 1 fm 24v01 - g a9646447 r ic1021 xxxx xx - p rll llll l ricyyw w p i n 1 3 . 9 0 0 . 1 0 6 . 0 0 0 . 2 0 4 . 9 0 0 . 1 0 0 . 1 0 0 . 2 5 1 . 3 5 1 . 7 5 0 . 3 3 0 . 5 1 1 . 2 7 0 . 1 0 m m 0 . 2 5 0 . 5 0 4 5 0 . 4 0 1 . 2 7 0 . 1 9 0 . 2 5 0 - 8 r e c o m m e n d e d p c b f o o t p r i n t 7 . 7 0 0 . 6 5 1 . 2 7 2 . 0 0 3 . 7 0 www.datasheet.co.kr datasheet pdf - http://www..net/
FM24V01 - 128kb i2c fram rev. 1.1 sept. 2011 page 14 of 14 revision history revision date summary 1 .0 10 / 2 0 /2010 initial release 1.1 9 /2 2 /2011 removed s/n ordering option. added note to t pu , t su: dat , and t high timing parameter s that apply when v dd < 2.7v . ordering information part number features operating voltage package fm 24v01 - g device id 2.0 - 3.6v 8 - pin green/rohs soic FM24V01 - gtr device id 2.0 - 3.6v 8 - pi n green/rohs soic, tape & reel www.datasheet.co.kr datasheet pdf - http://www..net/

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